The present invention relates generally to a semiconductor integrated memory device capable of storing therein a very large capacity data of gigabits or more. More specifically, the invention relates to a non-volatile semiconductor integrated memory device having a thin-film capacitor of a ferroelectric thin-film.
As it is required to increase the integrated density of a semiconductor integrated memory device to store a very large capacity data of gigabits or more, the memory cell size is still less, so that the capacities of conventional storage capacitors using oxide films are insufficient. Therefore, in recent years, memory devices using ferroelectric thin-films as storage capacitors (which will be hereinafter referred to as "ferroelectric memories") have been actively studied and developed, and a part of such memory devices have been put into practical use. The ferroelectric memory is non-volatile, and does not lose stored information even after a power source is turned off. In addition, if the thin-film of the ferroelectric memory is sufficiently thin, the spontaneous polarization thereof is quickly turned round, so that data can be written in and read out of the ferroelectric memory at a high speed which is substantially the same as that of a DRAM.
At present, the ferroelectric memories are classified broadly into two categories, first and second ferroelectric memories, which will be described below, on the basis of the use form of the ferroelectric thin-films.
The first ferroelectric memory uses a ferroelectric thin-film as a ferroelectric capacitor of a metal/ferroelectric/metal junction, and has a system for reading a charge when the polarization of the ferroelectric capacitor is turned round. The first ferroelectric memory has advantages in that it can be relatively easy to prepare the first ferroelectric memory since a ferroelectric capacitor is separately prepared, that the polarization of the first ferroelectric capacitor is easily retained since the potentials of both electrodes of the ferroelectric capacitor are equal to each other in a stand-by state, and that assuming that the minimum processed dimension is F, the area of one cell-to-one transistor (1T/1C) type cell similar to a DRAM is 8F.sup.2, and the area of a NAND type cell or a 1T/1C parallel-connected cell (Chain FRAM) is 4F.sup.2, so that the area of the memory cell can be decreased. Herein, the minimum processed dimension is 2F=L+S, assuming that the minimum line width and minimum space width of a pattern forming a semiconductor integrated memory device are L and S, respectively.
The second ferroelectric memory uses a ferroelectric thin-film as a ferroelectric gate transistor. This has a structure which uses a ferroelectric thin-film as a gate insulator film in place of a gate oxide film of a MOS-FET. The second ferroelectric memory is also called an "MFS (metal/ferroelectric/semiconductor)-FET". Since carriers sufficient to compensate the polarized charge of the ferroelectric thin-film are induced in the surface of the semiconductor, an inversion layer and an accumulation layer are formed in the polarized direction of the capacitor, so that the switching state of the transistor can be retained.
A particular excellent advantage of this device is that the polarized charge is not directly read out, and it can be amplified as a gain cell to be read out. Therefore, it is not required to retain storage using the absolute value of the polarized charge, and scaling can be achieved by a minimum dimension f if only the polarization density can be retained. Herein, the "minimum dimension f" means a so-called feature size, and it is generally given by L=S=f, or L=f, S=1.5f.
The aforementioned first ferroelectric memory using the ferroelectric thin-film as the ferroelectric capacitor has a disadvantage in that the amount of remnant polarization of the ferroelectric capacitor must be more than or equal to a certain absolute amount, so that scaling is difficult to be achieved by the minimum dimension f. The present reading using a ferroelectric capacitor is carried out by introducing the inverted charges of the capacitor into bit line capacities to carry out sense as the potential difference between bit lines. With scale down, the area of the capacitor and the amount of the inverted charge are decreased by F.sup.2, whereas the bit line capacity is substantially difficult to decrease, so that there is a limit to scaling.
On the other hand, the aforementioned second ferroelectric memory using the MFS-FET has many disadvantages. First, it is difficult to deposit a ferroelectric thin-film directly on Si. Because it is not easy to deposit an oxide ferroelectric thin-film, such as PZT (lead zirconate titanate: PbZr.sub.x Ti.sub.1-x O.sub.3), SBT (strontium bismuth tantalate: SrBi.sub.2 Ta.sub.2 O.sub.9) and BSTO (barium strontium titanate: Ba.sub.x Sr.sub.1-x TiO.sub.3), on Si, which is easy to oxidize, while maintaining the good crystallinity thereof. Also, although because there is a problem in that the majority of a voltage to be applied to the gate electrode of the MSF-FET is applied to a little SiO.sub.2 layer, which is produced in the interface between a ferroelectric thin-film and Si when the ferroelectric thin-film is deposited on Si, to increase the operating voltage, since the dielectric constant of the SiO.sub.2 layer is far less than that of the ferroelectric thin-film even if the SiO.sub.2 layer is thin, about a few nanometers. Moreover, because the interface level existing in the Si/ferroelectric interface, or the impurity level of the heavy metal in the ferroelectric diffusing in Si, serves as a trap of a channel of the MFS-FET to decrease the mobility of carriers and to vary the threshold voltage of the MFS-FET in accordance with the interface level density and the impurity level density, unlike an ideal Si/SiO.sub.2 interface. These problems are very important problems to be solved for high density integrated LSIs.
As a second disadvantage, there is a problem on a counter field applied to the ferroelectric thin-film. That is, the charge produced by the polarization of the ferroelectric is ideally equal to the charge induced on the Si surface, so that an accumulation layer and a depletion layer or an inversion layer are produced in a direction of polarization. At this time, the shifted part of the surface potential of Si is applied to the ferroelectric thin-film as a counter field. This counter field is applied in a direction in which the polarization is inverted, so that it is difficult to stably retain the polarization of the MFS-FET.
As a third disadvantage, there is a problem in that the memory cell size increases. When memory cells of MFS-FET are arranged in the form of a matrix to form a semiconductor integrated memory device, it is usually required to provide a write controlling transistor and a read controlling transistor in addition to an MFS-FET for retaining information therein. That is, in the case of the MFS-FET, a memory cell comprises three transistors (3T), and the area of the cell is greater than 18F.sup.2, so that the memory cell size is greater than that of the ferroelectric memory cell which uses a ferroelectric thin-film as a ferroelectric capacitor.
As described above, either of the ferroelectric capacitor of the first memory or the MFS-FET of the second memory has its merits and demerits, so that it is not possible to meet all of the demands that a high density integrated semiconductor is able to have small memory cells, be scaled, stably retain the polarization of the ferroelectric and be easily produced by a simple process.